1. Field of the Invention
The invention relates to an integrated memory circuit having a redundancy circuit for replacing an addressable memory area with a redundant memory area assigned to the redundancy circuit. The invention furthermore relates to a method for replacing an addressable memory area with a redundant memory area in an integrated memory circuit.
2. Description of the Related Art
An integrated memory circuit, in particular a DRAM memory circuit, is generally not free of defects after fabrication, i.e., defective memory cells are present throughout the memory chip, with the result that these memory chips thus cannot be used. In order to increase the yield of the integrated memory circuits after production, redundant memory areas are provided in addition to the memory areas in the integrated memory circuits.
After fabrication, the entire integrated memory circuit, including the redundant memory areas, is tested. The memory areas identified as defective are replaced by redundant memory areas. This is done with the aid of redundancy circuits which are respectively assigned to one of the redundant memory areas.
The redundancy circuits generally have a plurality of fuse storage elements, to which the address of the memory area which is to be replaced by the assigned redundant memory area can be written. The fuse storage elements are usually formed with the aid of laser fuses connected to a correspondingly assigned latch. The laser fuses are severed with the aid of a laser beam in a laser trimming process for the purpose of setting the addresses to be replaced of the memory areas which are to be replaced.
The laser fuses represent originally electrically conducting connecting lines which are vaporized with the aid of the laser beam, with the result that a previously electrically conducting connection is interrupted. The address to be replaced is thus set in such a way that a decision as to which of the laser fuses are severed and which of the laser fuses are retained unchanged is made for the laser fuses of the fuse storage elements.
The laser fuses are accessible only before the integrated memory circuits are housed. In other words, it is only after a front end test, i.e., testing of the integrated memory circuits at the wafer level, that it is possible to write settings with the aid of the laser trimming methods to the fuse storage elements. As soon as the integrated memory circuits are singulated and incorporated into the final housing, the laser fuses are no longer accessible. It is customary, therefore, to carry out a repair operation for the integrated memory circuits directly after the front end test at the wafer level.
There are cases, however, in which a plurality of repair steps are carried out. Firstly, in so-called “known good die” business, the integrated memory circuits can be supplied to the customer in a manner such that they are unpackaged or still situated on the wafer. In this case, the burn-in (i.e., the pre-aging) takes place with the non-housed integrated memory circuits. After or during the burn-in operation, a further functional test of the integrated memory circuit generally takes place, in the course of which, under certain circumstances, further defects may occur.
Since the integrated circuits continue to be accessible for a laser trimming process in this case, further repair steps may then follow. If it is ascertained in the course of the test operation after the burn-in operation that a redundant memory area which has been used for replacing a defective memory area likewise has a defect, the replacement of the conventional memory area by the redundant defective memory area can usually be reversed by means of a deactivation fuse storage element in that the deactivation fuse storage element is changed, i.e., the associated laser fuse is severed, and the defective memory area to be replaced is subsequently replaced by another, non-defective redundant memory area.
Secondly, the laser fuses will be replaced by electrical fuses (e-fuses) in the future. The e-fuses have the advantage that they can still be programmed even after housing, so that a renewed repair step can be carried out in the event of a defect occurring in a back end test operation, i.e., in the course of a test operation after housing.
The problem arises from the plurality of repair steps that the replacement of the defective memory area by the defective redundant memory area has to be reversed if, in the course of a subsequent repair step, a defect occurs on a redundant memory area which has already been used for repairing a defective memory area. For this purpose, as described above, a deactivation fuse storage element is usually provided for each redundancy circuit and, if the deactivation fuse storage element is changed permanently in its state, blocks the addressing of the defective redundant memory area if the address to be replaced is applied.
The deactivation fuse storage element provided for this purpose has to be provided for each of the redundant memory areas and requires a relatively significant area, irrespective of formation as a laser fuse storage element or as an e-fuse storage element.